Sinclair ZX80 / ZX81 Forums

[sirmorris]

I've added the pull-up resistors to the /m1, /iorq, /rd, /wr, /mreq but still the same instant crash on releasing the bus, I think.

I assert /busrq and wait for /busak. set up the data and address lines, assert /mreq and /wr.

I'll check the wiring and uC firmware as I'm sure it can work... Wilf's HS4 circuit hasn't actually been tested by the looks of it :/

C

[siggi]

Perhaps you could give us some details, which data should be transferred to which location?
Sometimes only one wrong bit might crash the Zeddy (or a nuclear power plant, or a Robo-Doc, or s..)

Siggi

PS: It's easy to crash a Zeddy, when you load a program, which has been saved in SLOW mode, during FAST mode ....

[sirmorris]

I'm attempting to write just a few bytes to screen RAM. It's just 10 bytes to the middle of the top line.

I've stripped the test interface back to the sockets, I'm going to approach the problem one step at a time.

1. Asserting and releasing /BUSRQ. If this doesn't work, game over.
2. Asserting and releasing /BUSRQ, having messed with address lines.
3. Asserting and releasing /BUSRQ, having messed with address and data lines.
4. Asserting and releasing /BUSRQ, having asserted /MREQ and /WR.

Let's see what happens.

C

[siggi]

I would try to write some well knows bytes (1,2,...255) to a safe location (>32K, 8-16K), where the Zeddy does not crash on wrong data (like when data with bit 6 set are put into the display file) and check the data there.

And /HALT also needs to be set so HIGH (the ULA uses that signal).

Does the zeddy crash? Or are wrong data written? Or happens nothing?

Siggi

[sirmorris]

Zeddy crashes. There are quite a few variables that needed checking and so I have stripped everything back to basics and will proceed one step at a time

I wonder if the data in zeddy's RAM was wrong and had bit 6 set? I will take your advice and try writing to 'safe' locations.

I'll also pull /halt high.

[siggi]

starting from the top - with /busrq - we see it get asserted. The signals here are all active when low.
/busak follows. This is the z80 confirming that it's sleeping. There is a period of silence in the trace and then you see little blips where the /wr line is asserted. This should poke values into RAM.

Nothing is "poked" into ram, because the /MREQ line is inactive and the ram ignores any /WR pulses.

Here is a Z80 timing diagram for memory read/write cycles. And that works in a Zeddy

MEM.jpg (70.25 KiB) Viewed 230 times

HTH Siggi